1. Field of the Invention
This invention relates to a semiconductor device, a method of fabricating the same, an RF power amplifier and a mobile communication system, and, more particularly, to an effective technique which can be applied to a heterojunction bipolar transistor used as a device in a super high-speed IC.
2. Prior Art
A Heterojunction Bipolar Transistor, or HBT, is a semiconductor device having high speed and low power consumption. Typically, such HBTs are built into RF power amplifier modules of mobile communication terminals such as cellular telephones.
In an HBT, a subcollector layer and collector layer are successively laminated on one surface (the main surface) of a semiconductor substrate, a base layer is partially formed on this collector layer, and an emitter layer comprising a wide bandgap semiconductor is partially formed on this base layer.
An InGaP/GaAs HBT is known in the art which offers little degradation and high reliability, using an InGaP layer as the emitter layer to suppress the drop of gain due to recombination of minority carriers between the emitter and the base. In these HBTs, carbon (C), which does not easily move even at large currents, is used as a dopant in a p-type base layer.
This structure is disclosed as an example in the xe2x80x9cInternational Electron Devices Meeting Digestxe2x80x9d, p.191, 1994 (High-Reliability InGaP/GaAs HBTs Fabricated Self-Aligned Process).
In this reference, an HBT is disclosed wherein a thin emitter layer is left on the base layer to improve reliability, a base electrode is formed thereon, and an (alloyed) ohmic electrode is formed via this thin emitter layer. During mesa-etching of the base part, the emitter layer, base layer and collector layer are etched by reactive ion etching (RIE) using the base electrode as a mask.
In Japanese Unexamined Patent Publication No. H9-102502, an HBT (GaAs type HBT wherein the emitter layer is InGaP) is disclosed wherein the base electrode, which comes in contact with the base layer, covers the edge of the emitter layer to suppress junction damage. In this construction, ohmic contact is obtained between the base electrode and base layer without the use of alloys.
Further, in Japanese Unexamined Patent Publication No. H9-36131, a technique (GaAs type HBT wherein the emitter is AlGaAs) is disclosed wherein, when the base layer is etched, wet etching is prolonged and the base-collector junction surface area is decreased by side etching to the underside of the base electrode in order to decrease the base-collector capacitance.
An identical technique for decreasing the base-collector capacitance is disclosed in Japanese Unexamined Patent Publication No. H8-195400.
As described in the above references, in order to achieve high speed in an AlGaAs/GaAs type HBT, it is important to decrease the base-collector junction area in order to decrease the base-collector capacitance. To decrease the base-collector capacitance, when the base layer (or base layer and collector layer) was etched in the prior art, a long etching time was allowed so that side etching proceeded to the underside of the base electrode (undercut technique).
The present invention pertains to developing an InGaP/GaAs type HBT wherein the emitter layer is InGaP. Also, in this HBT, high speed is desired as in the case of an AlGaAs/GaAs type HBT.
In order to decrease the base-collector capacitance, the base layer and collector layer were etched to the underside of the base electrode, but encounters the following problems were encountered in the course of this etching.
FIGS. 14-19 are diagrams describing a method of manufacturing a semiconductor device which the Inventor used prior to this application. As shown in FIG. 14, semiconductor layers are successively formed by epitaxial growth on one surface (the main surface) of a substrate (semiconductor substrate) 1 comprising semi-insulating GaAs. Starting from the substrate in an upward direction, these semiconductor layers comprise a subcollector layer 2 comprising n-type GaAs, a collector layer 3 comprising n type GaAs, a base layer 4 comprising p+ type GaAs, an emitter layer 5 comprising n-type InGaP, and an emitter cap layer 6 comprising n-type GaAs. The emitter cap layer 6 may comprise a plurality of layers.
As shown in FIG. 14, a first electrode layer 8a is formed comprising the lower layer of an emitter electrode on the semiconductor layer which is the emitter cap layer 6. Etching is performed using this first electrode layer 8a as an etching mask, and the emitter cap layer 6 is formed such that the periphery lies further inside than the edge of the first electrode layer 8a. The first electrode layer 8a may, for example, comprise WSi.
Next, as shown in FIG. 15, a photoresist mask is formed over the whole of the main surface of the semiconductor substrate 1, an electrode layer is formed, unnecessary parts of the electrode layer are selectively removed by a lift-off technique, and a second electrode layer 8b, which exactly overlaps the first electrode layer 8a, is formed on the emitter cap layer 6 so as to form an emitter electrode 7 comprising the first electrode layer 8a and the second electrode layer 8b. At the same time, a base electrode 9 is formed surrounding the emitter cap layer. As there is a large step between the surface of the emitter layer 5 and the surface of the first electrode layer 8a, the electrode layers break off in this step part, and as the edge of the first electrode layer 8a projects beyond the edge of the emitter cap layer 6, the base electrode 9 and the emitter cap layer 6 are situated at a fixed distance apart. These electrode layers are formed of Pt, Ti, Mo and Au or the like in a multi-layer arrangement.
Next, as shown in FIG. 16, a mask (etching mask) of an insulating film 10 is formed to cover the emitter electrode 7 and the base electrode 9, excepting the outer edge, and the InGaP emitter layer 5 is subjected to undercut etching by wet etching using hydrochloric acid as an etchant. As a result, the edge of the InGaP emitter layer 5 comes to be situated further inside than the edge of the base electrode 9.
Next, as shown in FIG. 17, the semiconductor layers comprising the base layer 4 and collector layer 3 are formed by undercut etching, i.e., wet etching using phosphoric acid as an etchant and using the aforesaid etching mask 10, base electrode 9, and emitter layer 5 as etching masks. Due to this undercut etching, the junction area between the base layer and collector layer is reduced, and the base-collector capacitance can be decreased.
However, in the aforesaid etching by hydrochloric acid, Ti and Mo, which are component materials of the base electrode become corroded causing degeneration of the electrode. Cracks appear in the mask 10 on the electrode due to the corrosion of Ti and Mo, and the InGaP emitter layer 5 between the cap layer 6 and the base electrode 9 is etched. All of these factors lead to a degeneration of performance.
Further, the InGaP layer around the base electrode 9 may not be completely removed and there may be InGaP etching residues (remnants 11), as shown in FIG. 18.
Further, in the wet etching using phosphoric acid, the remnants 11 act as a mask leading to etching defects 12 where the base layer and the collector layer under it are not etched, as shown in FIG. 19. As a result, the base-collector capacitance increases and the uniformity of the base-collector capacitance decreases. This impairs the performance and decreases the reproducibility of the heterojunction bipolar transistor.
It is therefore an object of this invention to provide a heterojunction bipolar transistor with high speed, and a method of fabricating the same.
It is a further object of this invention to provide a technique for reducing the degeneration of a base electrode and emitter layer during etching which is performed to reduce a base-collector junction area of the heterojunction bipolar transistor.
It is a further object of this invention to provide a technique for carrying out etching which is performed to reduce the base-collector junction area of the heterojunction bipolar transistor with high precision and good reproducibility.
It is yet a further object of this invention to provide an RF power amplifier incorporating an HBT having good characteristics and high reliability.
These and other novel features of this invention will become apparent from the following description and appended drawings.
The essential features of the invention disclosed in this application may be briefly described as follows:
(1) In a semiconductor device comprising a heterojunction bipolar transistor which includes a subcollector layer, collector layer, base layer, emitter layer and emitter cap layer successively formed in predetermined shapes on one surface of a semiconductor substrate, the transistor having a structure wherein an inner edge part of a base electrode overlaps the periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode, the emitter layer is selectively formed on the base layer, the base electrode extends from the peripheral part of the emitter layer to the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode. The semiconductor substrate is formed of a semi-insulating GaAs substrate, the subcollector layer and collector layer are formed of an n-type GaAs layer, the base layer is formed of a p-type GaAs layer, the emitter layer is formed of an n-type InGaP layer, and the emitter cap layer is formed of an n-type GaAs layer. The emitter layer formed of InGaP has a thickness of 15 to 30 nm. The cover part of the emitter electrode is formed of an electrode layer forming the base electrode. The base electrode is formed of Pt/Ti/Mo/Ti/Pt/Au, having Pt as the lowermost layer. Also, if the thickness of the InGaP emitter layer is tE, the thickness of the base layer is tB, and the thickness of the Pt of the lowermost layer of the base electrode is tPt, the relations tPtxe2x89xa72tE, and tB greater than 2tPt are satisfied.
This semiconductor device is fabricated by the following method:
This method of fabricating the semiconductor device, a heterojunction bipolar transistor is fabricated by successively forming semiconductor layers comprising a subcollector layer, collector layer, base layer, emitter layer and emitter cap layer on one surface of a semiconductor substrate. The subcollector layer, collector layer, base layer, emitter layer and emitter cap layer are formed by etching predetermined semiconductor layers of the semiconductor layers in a predetermined pattern, an emitter electrode is formed on the emitter layer, a base electrode is formed whereof an inner edge part overlaps the periphery of the emitter layer, a collector electrode is formed on the collector layer, and the base electrode is electrically connected to the base layer via an alloy layer by alloying the emitter layer under the base electrode.
This method comprises the steps of:
successively forming the semiconductor layers comprising the subcollector layer, collector layer, base layer, emitter layer and emitter cap layer on one surface of the semiconductor substrate;
selectively forming a first electrode layer comprising the emitter electrode on the semiconductor layer which is the emitter cap layer;
forming the emitter cap layer so that its periphery lies further inside than the edge of the emitter electrode by etching the semiconductor layer which is the emitter cap layer using the first electrode layer as an etching mask;
forming an etching mask to cover the first electrode layer comprising the emitter cap layer and the emitter electrode, and then forming the emitter layer by etching the semiconductor layer which is the emitter layer;
removing the etching mask, forming a photoresist mask on the whole of one surface of said semiconductor substrate, forming an electrode layer and lifting off unnecessary parts, forming the base electrode by an electrode layer extending from the periphery of the emitter layer to the semiconductor layer which is the base layer, and forming the emitter electrode by the first electrode layer and a second electrode layer comprising the electrode layer which exactly overlaps the first electrode layer; and
forming an etching mask so that the outer edge of the base electrode is exposed and the emitter layer and emitter electrode are covered, and undercut etching the semiconductor layers which are the base layer and collector layer.
The subcollector layer comprising an n-type GaAs layer, the collector layer comprising an n-type GaAs layer, the base layer comprising a p-type GaAs layer, the emitter layer comprising an n-type InGaP layer, and the emitter cap layer comprising an n-type GaAs layer are successively formed on one surface of a semiconductor substrate comprising a semi-insulating GaAs substrate. The emitter layer is etched by wet etching using hydrochloric acid as an etchant, and the collector layer and subcollector layer are etched by wet etching using phosphoric acid as an etchant. The emitter layer comprising InGaP is formed to a thickness of the order of 15-30 nm. The base electrode is formed from Pt/Ti/Mo/Ti/Pt/Au, having Pt as the lowermost layer. The layers are formed so that, if the thickness of the InGaP emitter layer is tE, the thickness of the base layer is tB, and the thickness of the Pt of the lowermost layer of the base electrode is tPt, the relations tPtxe2x89xa72tE, and tB greater than 2tpt are satisfied.
(2) In the heterojunction bipolar transistor having the construction of the aforesaid means (1), the edge of the base layer is situated further inside than the edge of the emitter layer, and the base electrode does not come in direct contact with the base layer.
In the method of fabricating the semiconductor device as described in the aforesaid means (1), when the base layer and the collector layer are subjected to undercut etching, the undercut etching is performed so that the edge of the base layer is situated further inside than the edge of the emitter layer, and the base electrode does not come in direct contact with the base layer.
(3) An RF power amplifier incorporating a heterojunction bipolar transistor of the aforesaid means (1) or (2).
(4) A mobile communication system incorporating the RF power amplifier of the aforesaid means (3).
According to the aforesaid means (1):
(a) As the InGaP emitter layer is etched with hydrochloric acid before forming the base electrode, the Mo or Ti of the base electrode is not easily corroded, and degeneration of the electrode does not easily occur.
It may be noted that corrosion of the base electrode does not occur during the etching with phosphoric acid, which is performed later.
(b) As the Ti or Mo is not easily corroded, surface degeneration of the base electrode does not easily occur, the mask on the electrode does not easily peel off, the InGaP emitter layer between the emitter cap layer and base electrode is not easily etched, and the impairment of the characteristics of the heterojunction bipolar transistor is reduced.
(c) As etching is not impaired by the substances produced by the corrosion of Ti or Mo, the InGaP emitter layer is etched to high precision according to the specifications of the etching mask, and the remnants of InGaP are not easily produced. As a result, undercut etching of the base layer and the collector layer by phosphoric acid can also be performed to high precision, and a base-collector capacitance can be formed according to design specifications. Therefore, a heterojunction bipolar transistor with very high speed can be provided.
(d) As corrosion of the base electrode does not easily occur and peeling of the etching mask does not easily occur during etching, the HBT fabrication process is stable, and as the yield is improved, the cost of manufacturing the semiconductor device can also be reduced.
(e) The base electrode is formed from the edge of the n-type InGaP emitter layer across the base layer, the n-type InGaP emitter layer under the base electrode is alloyed with the metal of the lowermost layer forming th e base electrode, and the base electrode an d base layer are thereby ohmically connected.
Further, on the side adjacent to the base-collector junction interface, the alloy layer is formed to a uniform depth which is less than the depth of the base layer, so the alloy layer does not come in contact with the collector layer, and the base-collector breakdown voltage of the device is maintained at a high level.
(f) As alloy is also formed in the surface direction of the n type InGaP emitter layer, the distance between the intrinsic region of the base layer part immediately beneath the emitter layer and the alloy layer is less than the distance to the base electrode, and as a result the base resistance RB is decreased, and the device THBT) can operate at high speed.
According to the aforesaid means (2), in addition to the effect of the aforesaid means (1), the edge of the base layer is also closer to the center of the emitter layer so that the base electrode does not come in direct contact with the base layer, and a greater reduction of base-collector capacitance can be obtained.
According to the aforesaid means (3), an RF power amplifier having satisfactory speed characteristics and high reliability can be provided.
According to the aforesaid means (4), as the RF power amplifier operates at a high speed, a larger volume of information can be transmitted.